$tribuf

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Simulation model (Verilog)

Listing 359 simlib.v:1460

module \$tribuf (A, EN, Y);

    parameter WIDTH = 0;

    input [WIDTH-1:0] A;
    input EN;
    output [WIDTH-1:0] Y;

    assign Y = EN ? A : 'bz;

endmodule

Note

This page was auto-generated from the output of help $tribuf.