$_ALDFF_NP_#
A negative edge D-type flip-flop with positive polarity async load.
Truth table: D C L AD | Q
----------+---
- - 1 a | a
d \ - - | d
- - - - | q
Simulation model (Verilog)#
module \$_ALDFF_NP_ (D, C, L, AD, Q);
input D, C, L, AD;
output reg Q;
always @(negedge C or posedge L) begin
if (L == 1)
Q <= AD;
else
Q <= D;
end
endmodule
Note
This page was auto-generated from the output of
help $_ALDFF_NP_
.