$assume

No help message for this cell type found.

Simulation model (Verilog)

Listing 276 simlib.v:1703

module \$assume (A, EN);

    input A, EN;

    `ifndef SIMLIB_NOCHECKS
    always @* begin
        if (A !== 1'b1 && EN === 1'b1) begin
            $display("Assumption %m failed!");
            $stop;
        end
    end
    `endif

endmodule

Note

This page was auto-generated from the output of help $assume.