$_DFFE_PP0N_

A positive edge D-type flip-flop with positive polarity reset and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 0
                d / - 0 | d
                - - - - | q

Simulation model (Verilog)

Listing 145 simcells.v:1172

module \$_DFFE_PP0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C or posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

Note

This page was auto-generated from the output of help $_DFFE_PP0N_.