$mod#
$mod (A, B, Y)
Modulo/remainder of division with truncated result (rounded towards 0).
Invariant: $div(A, B) * B + $mod(A, B) == A
Simulation model (Verilog)#
module \$mod (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) % $signed(B);
end else begin:BLOCK2
assign Y = A % B;
end
endgenerate
endmodule
Note
This page was auto-generated from the output of
help $mod
.