$_DLATCHSR_NNN_#
A negative enable D-type latch with negative polarity set and negative polarity reset.
Truth table: E S R D | Q
---------+---
- - 0 - | 0
- 0 - - | 1
0 - - d | d
- - - - | q
Simulation model (Verilog)#
module \$_DLATCHSR_NNN_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
Note
This page was auto-generated from the output of
help $_DLATCHSR_NNN_
.