$dlatch

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Simulation model (Verilog)

Listing 290 simlib.v:2216

module \$dlatch (EN, D, Q);

    parameter WIDTH = 0;
    parameter EN_POLARITY = 1'b1;

    input EN;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;

    always @* begin
        if (EN == EN_POLARITY)
            Q = D;
    end

endmodule

Note

This page was auto-generated from the output of help $dlatch.