$equiv

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Simulation model (Verilog)

Listing 293 simlib.v:1829

module \$equiv (A, B, Y);

    input A, B;
    output Y;

    assign Y = (A !== 1'bx && A !== B) ? 1'bx : A;

    `ifndef SIMLIB_NOCHECKS
    always @* begin
        if (A !== 1'bx && A !== B) begin
            $display("Equivalence failed!");
            $stop;
        end
    end
    `endif

endmodule

Note

This page was auto-generated from the output of help $equiv.