$overwrite_tag#

No help message for this cell type found.

Simulation model (Verilog)#

Listing 331 simlib.v:2772#
module \$overwrite_tag (A, SET, CLR);

    parameter TAG = "";
    parameter WIDTH = 0;

    input [WIDTH-1:0] A;
    input [WIDTH-1:0] SET;
    input [WIDTH-1:0] CLR;

endmodule

Note

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