$overwrite_tag#
No help message for this cell type found.
Simulation model (Verilog)#
module \$overwrite_tag (A, SET, CLR);
parameter TAG = "";
parameter WIDTH = 0;
input [WIDTH-1:0] A;
input [WIDTH-1:0] SET;
input [WIDTH-1:0] CLR;
endmodule
Note
This page was auto-generated from the output of
help $overwrite_tag
.