$mux

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Simulation model (Verilog)

Listing 324 simlib.v:1321

module \$mux (A, B, S, Y);

    parameter WIDTH = 0;

    input [WIDTH-1:0] A, B;
    input S;
    output [WIDTH-1:0] Y;

    assign Y = S ? B : A;

endmodule

Note

This page was auto-generated from the output of help $mux.