$_NMUX_

A 2-input inverting MUX gate.

Truth table:    A B S | Y
               -------+---
                0 - 0 | 1
                1 - 0 | 0
                - 0 1 | 1
                - 1 1 | 0

Simulation model (Verilog)

Listing 208 simcells.v:244

module \$_NMUX_ (A, B, S, Y);
    input A, B, S;
    output Y;
    assign Y = S ? !B : !A;
endmodule

Note

This page was auto-generated from the output of help $_NMUX_.