$slice

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Simulation model (Verilog)

Listing 350 simlib.v:1291

module \$slice (A, Y);

    parameter OFFSET = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    assign Y = A >> OFFSET;

endmodule

Note

This page was auto-generated from the output of help $slice.