$_SDFFCE_PP1N_#
A positive edge D-type flip-flop with positive polarity synchronous set and negative polarity clock enable (with clock enable having priority).
Truth table: D C R E | Q
---------+---
- / 1 0 | 1
d / - 0 | d
- - - - | q
Simulation model (Verilog)#
module \$_SDFFCE_PP1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (E == 0) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
end
endmodule
Note
This page was auto-generated from the output of
help $_SDFFCE_PP1N_
.