$_DLATCH_P_#
A positive enable D-type latch.
Truth table: E D | Q
-----+---
1 d | d
- - | q
Simulation model (Verilog)#
module \$_DLATCH_P_ (E, D, Q);
input E, D;
output reg Q;
always @* begin
if (E == 1)
Q <= D;
end
endmodule
Note
This page was auto-generated from the output of
help $_DLATCH_P_
.