$_MUX_

A 2-input MUX gate.

Truth table:    A B S | Y
               -------+---
                a - 0 | a
                - b 1 | b

Simulation model (Verilog)

Listing 206 simcells.v:225

module \$_MUX_ (A, B, S, Y);
    input A, B, S;
    output Y;
    assign Y = S ? B : A;
endmodule

Note

This page was auto-generated from the output of help $_MUX_.