$_DFFE_NP_

A negative edge D-type flip-flop with positive polarity enable.

Truth table:    D C E | Q
               -------+---
                d \ 1 | d
                - - - | q

Simulation model (Verilog)

Listing 139 simcells.v:641

module \$_DFFE_NP_ (D, C, E, Q);
    input D, C, E;
    output reg Q;
    always @(negedge C) begin
        if (E) Q <= D;
    end
endmodule

Note

This page was auto-generated from the output of help $_DFFE_NP_.