$anyinit

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Simulation model (Verilog)

Listing 273 simlib.v:1788

module \$anyinit (D, Q);

    parameter WIDTH = 0;

    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;

    initial Q <= 'bx;

    always @(`SIMLIB_GLOBAL_CLOCK) begin
        Q <= D;
    end

endmodule

Note

This page was auto-generated from the output of help $anyinit.