$set_tag

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Simulation model (Verilog)

Listing 345 simlib.v:2742

module \$set_tag (A, SET, CLR, Y);

    parameter TAG = "";
    parameter WIDTH = 0;

    input [WIDTH-1:0] A;
    input [WIDTH-1:0] SET;
    input [WIDTH-1:0] CLR;
    output [WIDTH-1:0] Y;

    assign Y = A;

endmodule

Note

This page was auto-generated from the output of help $set_tag.