$_DFFE_PP1P_

A positive edge D-type flip-flop with positive polarity set and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 1
                d / - 1 | d
                - - - - | q

Simulation model (Verilog)

Listing 148 simcells.v:1244

module \$_DFFE_PP1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C or posedge R) begin
        if (R == 1)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

Note

This page was auto-generated from the output of help $_DFFE_PP1P_.