$_OAI3_

A 3-input Or-And-Invert gate.

Truth table:    A B C | Y
               -------+---
                0 0 0 | 1
                0 0 1 | 1
                0 1 0 | 1
                0 1 1 | 0
                1 0 0 | 1
                1 0 1 | 0
                1 1 0 | 1
                1 1 1 | 0

Simulation model (Verilog)

Listing 211 simcells.v:374

module \$_OAI3_ (A, B, C, Y);
    input A, B, C;
    output Y;
    assign Y = ~((A | B) & C);
endmodule

Note

This page was auto-generated from the output of help $_OAI3_.