$_DFFSRE_PNNN_

A positive edge D-type flip-flop with negative polarity set, negative polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 0 - - | 0
                - 0 - - - | 1
                / - - 0 d | d
                - - - - - | q

Simulation model (Verilog)

Listing 158 simcells.v:1985

module \$_DFFSRE_PNNN_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(posedge C, negedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
            else if (E == 0)
            Q <= D;
    end
endmodule

Note

This page was auto-generated from the output of help $_DFFSRE_PNNN_.