$bwmux

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Simulation model (Verilog)

Listing 279 simlib.v:1667

module \$bwmux (A, B, S, Y);

    parameter WIDTH = 0;

    input [WIDTH-1:0] A, B;
    input [WIDTH-1:0] S;
    output [WIDTH-1:0] Y;

    genvar i;
    generate
        for (i = 0; i < WIDTH; i = i + 1) begin:slices
            assign Y[i] = S[i] ? B[i] : A[i];
        end
    endgenerate

endmodule

Note

This page was auto-generated from the output of help $bwmux.