$initstate

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Simulation model (Verilog)

Listing 303 simlib.v:1744

module \$initstate (Y);

    output reg Y = 1;
    reg [3:0] cnt = 1;
    reg trig = 0;

    initial trig <= 1;

    always @(cnt, trig) begin
        Y <= |cnt;
        cnt <= cnt + |cnt;
    end

endmodule

Note

This page was auto-generated from the output of help $initstate.