$_NOT_

An inverter gate.

Truth table:    A | Y
               ---+---
                0 | 1
                1 | 0

Simulation model (Verilog)

Listing 210 simcells.v:56

module \$_NOT_ (A, Y);
    input A;
    output Y;
    assign Y = ~A;
endmodule

Note

This page was auto-generated from the output of help $_NOT_.