Internal formats# Format overview The RTL Intermediate Language (RTLIL) RTLIL identifiers RTLIL::Design and RTLIL::Module RTLIL::Cell and RTLIL::Wire RTLIL::SigSpec RTLIL::Process RTLIL::Memory RTLIL text representation Lexical elements Characters Identifiers Values Strings Comments File Autoindex statements Modules Attribute statements Signal specifications Connections Wires Memories Cells Processes Switches Syncs Internal cell library RTL cells Unary operators Binary operators Multiplexers Registers Memories Finite state machines Coarse arithmetics Specify rules Formal verification cells Debugging cells Gates