The following commands are executed by this synthesis command:
begin:
read_verilog -lib +/greenpak4/cells_sim.v
hierarchy -check -top <top>
flatten: (unless -noflatten)
proc
flatten
tribuf -logic
coarse:
synth -run coarse
fine:
extract_counter -pout GP_DCMP,GP_DAC -maxwidth 14
clean
opt -fast -mux_undef -undriven -fine
memory_map
opt -undriven -fine
techmap -map +/techmap.v -map +/greenpak4/cells_latch.v
dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib
opt -fast -noclkinv -noff
abc -dff -D 1 (only if -retime)
map_luts:
nlutmap -assert -luts 0,6,8,2 (for -part SLG46140V)
nlutmap -assert -luts 2,8,16,2 (for -part SLG46620V)
nlutmap -assert -luts 2,8,16,2 (for -part SLG46621V)
clean
map_cells:
shregmap -tech greenpak4
dfflibmap -liberty +/greenpak4/gp_dff.lib
dffinit -ff GP_DFF Q INIT
dffinit -ff GP_DFFR Q INIT
dffinit -ff GP_DFFS Q INIT
dffinit -ff GP_DFFSR Q INIT
iopadmap -bits -inpad GP_IBUF OUT:IN -outpad GP_OBUF IN:OUT -inoutpad GP_OBUF OUT:IN -toutpad GP_OBUFT OE:IN:OUT -tinoutpad GP_IOBUF OE:OUT:IN:IO
attrmvcp -attr src -attr LOC t:GP_OBUF t:GP_OBUFT t:GP_IOBUF n:*
attrmvcp -attr src -attr LOC -driven t:GP_IBUF n:*
techmap -map +/greenpak4/cells_map.v
greenpak4_dffinv
clean
check:
hierarchy -check
stat
check -noinit
blackbox =A:whitebox
json:
write_json <file-name>